[LGPR] Publication Success Series- Dr Shirly A Edward in Engineering Letters-International Association of Engineers

#LGPR #SCI #PublicationSuccess #EICompendex

Dr Shirly A Edward, LGPR Postdoctoral Candidate at LUC Malaysia has published in the Engineering Letters.

Engineering Letters 34(6) (2026)

Journal Indexes: Impact factor 0.6 | Cite Score 2.5

Indexing: SCOPUS | ESCI | EI Compendex | Web of Science Core Collection

H-Index: 27

Aims & Scope

Engineering Letters is a scholarly peer-reviewed gold open access academic journal from the International Association of Engineers. The journal covers the frontier issues in engineering and computer science and their applications in business, industry and other subjects. The topics covered include artificial intelligence, bioinformatics, chemical engineering, computational statistics, database, data mining, electrical engineering, electronics, engineering mathematics, engineering physics, environmental engineering, financial engineering, hardware systems, imaging engineering, industrial engineering, information engineering, internet computing, mechanical engineering, networking, operations research, scientific computing, software engineering, telecommunications, and their applications.

The open-access journal is accessible to accredited universities and government libraries. All the papers in the journal are also available freely with online full-text content and permanent worldwide web links. The abstracts will be indexed and available at major academic databases such as Scopus, EI Compendex, and Clarivate (formerly Thomson Reuters) Emerging Sources Citation Index (ESCI) in the Web of Science Core Collection, which is covered by the annual Journal Citation Reports (JCR) with the Journal Impact Factor (JIF).

• Frequency: 12 issues per year

• ISSN: 1816-0948 (online version); 1816-093X (print version)

• Subject Category: Computer science and engineering

• Published by: International Association of Engineers

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Analog/RF Performance Evaluation of Junctionless SOI FinFETs with Single, Double, and Triple Material Gates

Shirly A Edward

Lincoln Global Postdoctoral Research (LGPR) Program, Lincoln University College, Petaling Jaya 47301, Selangor Darul Ehsan, Malaysia

R. Linie Sharon

Department of Electronics and Communication Engineering, SRM Institute of Science and Technology Vadapalani Campus, Chennai, 600026, India

P Nagarajan

Department of Electronics and Communication Engineering, SRM Institute of Science and Technology Vadapalani Campus, Chennai, 600026, India

Rajesh Dey

Gopal Narayan Singh University, Bihar- India

Sai Kiran Oruganti

Lincoln Global Postdoctoral Research (LGPR) Program, Lincoln University College, Petaling Jaya 47301, Selangor Darul Ehsan, Malaysia

https://www.engineeringletters.com/issues_v34/issue_6/EL_34_6_31.pdf

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Abstract: This paper presents a comprehensive performance analysis of single, double, and triple material gate (SMGJL, DMGJL, TMGJL) Junctionless SOI FinFETs for Analog and RF applications using Technology Computer-Aided Design (TCAD) simulations at a 30 nm gate length. This study investigates key performance metrics, including Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), ON current (Ion), OFF current (Ioff), Ion/Ioff ratio, transconductance (gm), output conductance (gd), cut-off frequency (fT), and maximum oscillation frequency (fmax) for three different gate structures. The junctionless structure, along with SOI technology, enables simplified fabrication, improved electrostatic control, and reduced leakage currents. The simulation results indicate that the TMGJL FinFET exhibits superior performance, achieving the lowest SS (59.99mV/dec), highest Ion/Ioff ratio (6.11×10), and enhanced RF figures of merit (fT = 121.98GHz, fmax = 471.16GHz), making it highly suitable for next-generation low-power and high-frequency integrated circuits. Furthermore, the inverter circuit designed using the TMGJL FinFET exhibits high noise margin (NMH) of 0.500 V and low noise margin (NML) of 0.287 V, from the voltage transfer characteristics, indicating robust noise immunity of the simulated TMGJL FinFET. The comparative analysis demonstrates the advantages of multi-material gate engineering, with the TMGJL structure providing the best trade-off among switching behaviour, current drive capability, and RF/Analog performance. © 2026, International Association of Engineers. All rights reserved.